1. Field of the Invention
Embodiments of the invention generally relate to the field of semiconductor manufacturing processes, more particular, to methods for dopant activation within silicon-containing films forming semiconductor devices.
2. Description of the Related Art
Integrated circuits may include more than one million micro-electronic field effect transistors (e.g., complementary metal-oxide-semiconductor (CMOS) field effect transistors) that are formed on a substrate (e.g., semiconductor wafer) and cooperate to perform various functions within the circuit. The transistors can include semiconductor gates disposed between source and drain regions. In the formation of integrated circuit structures, and particularly in the formation of MOS devices using polysilicon gate electrodes, it has become the practice to provide a metal silicide layer over the polysilicon gate electrode and over the source and drain regions of the silicon substrate to facilitate lower resistance and improve device performance by electrically connecting the source and drain regions to metal interconnects. In a silicidation process, the source, drain and polysilicon gate resistances are reduced by forming a highly conductive overlayer and reducing the contact resistance by increasing the effective contact area of the source and drain with the subsequently formed metal interconnects.
Typically, after dopants have been implanted into the source and drain regions, a thermal activation process is performed prior to the silicidation process. The thermal activation process provides thermal energy sufficient to activate the implanted dopants and enable a defined source/drain junction to be formed. The increase of active dopants in the active regions improves device performance while insufficient activation of the dopants may result in high series resistance and low device speed. Conventional thermal activation processes are performed by a rapid thermal processing (RTP) and/or spike annealing. Recently, laser annealing has been developed to meet the high dopant activation requirements of 65 nm features.
However, during formation of the metal silicide layer, the agglomeration and irregular growth of the metal silicide layer may cause dopants to be segregated and accumulated on the silicon side of the interface of the silicon and silicide layer, resulting in so-called “snow-plow effect”. The dopant migration in the source/drain regions may influence the crystallinity in the active regions and contribute a modification of the interface dipole. The modification of the interface dipole in the interface area resulting from the snow-plow effect may adversely affect the electrical performance, such as working function shift, of the semiconductor devices and result in a retardation of silicidation kinetic. The non-uniform dopant concentration at the interface area may also increase contact resistance, thereby deteriorating overall device speed and performance.
Therefore, there is a need for an improved method for fabricating CMOS devices.